Decoupling capacitors are commonly employed in integrated circuit designs to reduce noise interference. As a general rule, an increase in capacitance density is desirable, and chip designers are often faced with the difficult task of trying to achieve the largest capacitance possible for a fixed design area on a chip. This challenge is further exacerbated by current trends towards smaller feature sizes in circuit designs. Thus, the available design areas are also shrinking in size.
Therefore, techniques that increase the capacitance density for a fixed design area on a chip, would be desirable.